Gentian is software for multi-GPU production servers. It extends inference and training on one node or several, and runs on the NVIDIA hardware a customer already owns. The integrations demonstrated today are vLLM for inference and Megatron for training; the attachment point is not specific to either. No replacement platform or special hardware mode is required.
Gentian is named after Gentiana, a wildflower widespread across Europe, typical of the Swiss Alps, and used in traditional medicine.
Three product capabilities
Longer context
On eight NVIDIA B200 GPUs, Gentian served 1.3 million tokens in both fp16
and fp32, with the numerical gate passing at a residual of 7.23e-6 against a tolerance of
0.03. The conventional
all_gather path exhausted device memory at about half a million.
This is a capacity result, not a speed result. That 1.3-million-token point is a demonstrated floor, not a ceiling: the reference oracle itself ran out of memory before the next rung could be tested. The context-parallel value surface begins where tensor parallelism exceeds the number of KV heads, or with MLA; no benefit is claimed for an ordinary Llama-70B TP=8 configuration on this mechanism alone.
Cached retrieval
On Llama-3.3-70B at TP=8 on 8×NVIDIA H100, with
gpu-memory-utilization=0.85, Gentian's canonical policy held prefix-cache hit rate in a band of
95.29–98.91% across a sweep from 10 to 48 documents. Over the same sweep, LRU declined from
12.52% at 10 documents to 2.67–2.92% at 48, the two replicates at that size.
That is a hit-rate stability result. It is not a throughput ratio or speedup. The value is the server-side deployment model: the vLLM plugin applies a consistent ordering without an engine fork, client changes, or tenant coordination. The ordering algorithm itself is not claimed as novel.
A record for every answer
Each answer can carry a signed record. For one real vLLM response on stock, non-confidential NVIDIA Blackwell hardware, a cybiont-controlled key signed only after an enrolled NVIDIA device answered a fresh challenge bound to that response. The record remained independently verifiable after the signer and GPU path were gone.
That result proves device presence at authorisation. It does not prove that the GPU executed the response or was physically local. Firmware measurements were not appraised, revocation was not checked, presence was not continuous, and no performance property is established. The model, input, and response fields are signed commitments, not execution attestation.
Get the valid and tampered records and run the offline verifier.
The capacity and cache figures above are reported measurements; their raw bundles are not published on this site. The response-record package is the result a visitor can independently rerun here.
Integration surface and its boundary
- vLLM inference: a server-side plugin path with no engine fork or client changes, plus the retained-sidecar response-record attachment demonstrated by the public package.
- Megatron training: an attention-spec-slot adapter invoked through the real Megatron-Core
GPTModel, with a training record component. - Topology: the product surface covers single- and multi-node multi-GPU servers. The public numerical results on this page are named eight-GPU, single-node cells.
Gentian is ready for a paid customer integration pilot with defined workloads, devices, claims, and acceptance criteria, leading toward production qualification.
Architecture validated beyond software
Gentian Software is the product today, running on the NVIDIA systems you already operate. The same architecture exists in hardware as well, twice over: taken through physical design on a 7 nm process, and running a real language model on an FPGA. Both embodiments produce correct output, which turns "do these invariants survive contact with silicon" from a question into two artefacts.
Physical design. Nineteen logic macros taken to DRC-clean GDS on ASAP7, an academic 7 nm PDK, across 6.03 mm² of logic floorplan.
A transformer runs in the hardware. On AWS F2 (VU47P), the narrow-streaming mesh executes TinyLlama-1.1B end to end — all twenty-two decoder layers across four mesh nodes, with every sublayer in the datapath: RMSNorm, Q/K/V projections, RoPE, KV-cache writes, grouped-query attention, residuals, SwiGLU, then the final norm, logits projection and sampling. At 125 MHz, post-route timing closed, zero failing endpoints of 1,096,820.
The token it emits matches the reference implementation exactly. That match is how a twenty-two-layer path is shown to be right end to end — it is the evidence, not the achievement.
The hardware programme remains a separate, longer-horizon research track; the research index carries its public scope.
Technical scope. ASAP7 is an academic PDK, SRAM was black-boxed, and this is not a tape-out. The FPGA result is a functional bring-up, not a performance vehicle: no throughput or latency figure follows from it. Separately — a different capability, not part of this inference path — the distributed fold is host-orchestrated, using FPGA-produced observations. The fold does not run on the FPGA.
Qualify a workload
An evaluation starts from one named workload: the model, the device count and topology, the constraint you are hitting now, and what would count as a result. From that we establish whether the evidence above applies to your case, and agree the claim and its acceptance criteria in writing before any integration work begins. What comes back is a scoped integration assessment and a measured outcome under the agreed conditions.
Write to pilot@cybiont.com with those five things, or ask whatever question stands between you and them.